Journal: Sensors (Basel, Switzerland)

Article Title: Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers

doi: 10.3390/s24248001

Figure Lengend Snippet: Comparison of the Simulink OR Mask ( left ) with the full-precision MATLAB reference ( right ).

Article Snippet: Results from hardware simulation are compared against high-precision floating-point MATLAB implementations.

Techniques: Comparison

Journal: Sensors (Basel, Switzerland)

Article Title: Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers

doi: 10.3390/s24248001

Figure Lengend Snippet: Comparison of the Simulink AND Mask ( left ) with the full-precision MATLAB reference ( right ).

Article Snippet: Results from hardware simulation are compared against high-precision floating-point MATLAB implementations.

Techniques: Comparison

Journal: Sensors (Basel, Switzerland)

Article Title: Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers

doi: 10.3390/s24248001

Figure Lengend Snippet: Comparison of the Simulink OR Mask ( left ) with the full-precision MATLAB reference ( right ).

Article Snippet: The simulation was performed either by MATLAB R2022a HDL Coder or MATLAB R2022a Simulink (MathWorks), and the results were compared numerically to the outputs of the original MATLAB algorithm, which uses floating-point double-precision data types.

Techniques: Comparison

Journal: Sensors (Basel, Switzerland)

Article Title: Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers

doi: 10.3390/s24248001

Figure Lengend Snippet: Comparison of the Simulink AND Mask ( left ) with the full-precision MATLAB reference ( right ).

Article Snippet: The simulation was performed either by MATLAB R2022a HDL Coder or MATLAB R2022a Simulink (MathWorks), and the results were compared numerically to the outputs of the original MATLAB algorithm, which uses floating-point double-precision data types.

Techniques: Comparison

Journal: Sensors (Basel, Switzerland)

Article Title: An Overview of Machine Learning within Embedded and Mobile Devices–Optimizations and Applications

doi: 10.3390/s21134412

Figure Lengend Snippet: Embedded FPGAs: optimization and throughput.

Article Snippet: 2015 , [ ] , Deep Learning FPGA Architecture , The acceleration of deep learning inference, particularly to large-scale networks using an FPGA, is considered in this work. The research exploits the high performance, reduced power consumption, and low-cost advantages of employing the FPGA to accelerate the prediction process of a DNN model. The research was limited to the prediction process. The Accelerator Architecture proposed by the research contained a direct memory access module, a deep learning module with an ARM Cortex CPU. To tackle the challenge of mapping in large neural networks owing to constrained computational resources, a time-sharing computational technique is adopted in the execution of data fragments that have been previously partitioned using the tiling technique. , The performance of the architecture is improved by cache reuse effected by introducing a Block RAM module. Furthermore, the throughput was increased by incorporating a pipelining methodology in the DL module. To address the flexibility challenge of the FPGAs, a software library is proposed to make the system user-accessible. The performance of the proposed model is measured by comparing the results with a MATLAB-based Core2 CPU baseline. The results show improved performance in power consumption and data throughput , The tiling technique introduces some accuracy errors in computation. The research adopted a high floating-point computation. However, a low fixed-point precision approximation of the DNN model if introduced, could further save memory usage and improve performance..

Techniques: Blocking Assay, Software, Activation Assay, Introduce, High Throughput Screening Assay